GATE Electronics and Communications (EC) 2019 Solved Paper

A CMOS inverter, designed to have a midpoint voltage ${\mathit{V}}_{\mathit{I}}$ equal to half of ${\mathit{V}}_{\mathit{d}\mathit{d}}$, as shown in the figure, has the following parameters: ${\mathit{V}}_{\mathit{d}\mathit{d}}=3\mathit{V}$
${\mathit{\mu }}_{\mathit{n}}{\mathit{C}}_{\mathit{o}\mathit{x}}=100\mathit{\mu }\mathit{A}/{\mathit{V}}^2;{\mathit{V}}_{\mathit{t}\mathit{n}}=0.7\mathit{V}$ for nMOS
${\mathit{\mu }}_{\mathit{n}}{\mathit{C}}_{\mathit{o}\mathit{x}}=40\mathit{\mu }\mathit{A}/{\mathit{V}}^2;|{\mathit{V}}_{\mathit{t}\mathit{p}}|=0.9\mathit{V}$ for pMOS
The ratio of ${\left(\frac{\mathit{W}}{\mathit{L}}\right)}_{\mathit{n}}$ to ${\left(\frac{\mathit{W}}{\mathit{L}}\right)}_{\mathit{p}}$ is equal to _______________ (rounded off to 3 decimal places).